1. Field of the Invention
The present invention relates to a semiconductor memory device provided with error correcting function.
2. Description of the Prior Art
In the semiconductor memory device in general, when information data are written in the memory cell array, error correction data (parity data) are stored additionally. That is, when the information data are read from the memory cell array, inspection as to whether the data contents are correct or not (parity check) is effected. When an error is found, the read data are outputted after having been corrected.
The semiconductor memory device in general is provided with an error correction data forming circuit and an error inspecting and correcting circuit.
For example, on the basis of the information data of 8 bits, the error correction data forming circuit forms error correction data of 4 bits. The error correction data forming circuit accepts predetermined data of at least one bit (previously determined according to the system) from the 8-bit information data, and processes the accepted data in accordance with a predetermined calculation to form a bit value. Thus, the information data of 8 bits and the error correction data of 4 bits, the total of 12 bits, are stored in the memory cell array.
The error inspecting correcting circuit processes the received 12-bit data in accordance with a predetermined calculation to inspect whether an error of the 8-bit information data is present or absent and further to find the error bit, if any. In the case of the absence of error, the received information data are outputted to an input/output buffer as they are (as path-through data). In the case of the presence of an error bit, the error bit is inverted and then outputted to the input/output buffer.
As described above, the error correcting function can provide a system resistant against noise, without interrupting the information calculation processing in such a case where one bit of the 8-bit information data is not transmitted correctly.
On the other hand, the semiconductor memory circuit device must be tested for operation and evaluated for the performance before shipment, in order to secure the reliability of the products using the semiconductor memory device.
In the conventional semiconductor device, however, there exists a problem when tested in accordance with a certain test method.
For instance, there exists such a test method that the operation test is evaluated by first storing a 12-bit alternate test data pattern such as "0101 . . . 0101" in the memory cell array and then by reading these stored 12-bit data, as one method of testing the semiconductor memory device.
In the above-mentioned semiconductor memory device, however, since the correction data stored in an error correction data storing area of the memory cell array are perfectly dependent upon the information data, the above-mentioned alternate pattern cannot be stored as one word in a single write cycle.
In other words, for example, the error correction data forming circuit randomly takes 5 bits from the 8 bits of information data and generates a "1" if the number of "1"s indicated by the 5 bits is an odd number, whereas it generates a "0" if there are an even number of "1"s. By repeating this process four times, the error correction data forming circuit forms an error correction data of 4 bits.
Therefore, it possibly happens that when the test data pattern such as "0101 . . . 0101" is applied to the semiconductor memory device), although "01010101" can be stored in an information data storing area of the memory cell array, the data stored in the error correction data storing area becomes "0110" for example. In other words, in spite of the fact that the 8-bit data of one word is composed of alternate bits, the remaining 4-bit data is not composed of alternate bits.
Therefore, information data must be inputted and stored in the error correction data storing area of the memory cell array, so that an alternate bit pattern can be obtained, in another write cycle different from the cycle in which information data are stored in the information data storing area.
Consequently, since two write cycles are required for one word test, in the case of the device of relatively low operation speed or of a large capacity (e.g., E.sup.2 PROM), a relatively long test time is inevitably required.
In addition, since the data itself stored in the error correction data storing area will not be outputted to the outside and therefore cannot be confirmed, it is difficult to evaluate the performance even when abnormal operation is recognized.